HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 526

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Pin Function Controller (PFC)
16.3.11 Port F IO Register (PFIOR)
The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 12 pins in port F. Bits PF11IOR to PF0IOR correspond to pins
PF11/BREQ/PULS7 to PF0/IRQ0. PFIOR is enabled when port F pins function as general
input/output pins (PF11 to PF0) or the PF8/SCK2/PULS4 pin has the serial clock function
(SCK2), and is disabled otherwise.
When port F pins function as PF11 to PF0 or include the SCK2 function, a pin becomes an output
when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0.
PFIOR is initialized to H'F000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.12 Port F Control Registers 1 and 2 (PFCR1, PFCR2)
Port F control registers 1 and 2 (PFCR1, PFCR2) are 16-bit readable/writable registers that select
the functions of the 12 multiplex pins in port F. PFCR1 selects the functions of the pins for the
upper 4 bits in port F, and PFCR2 selects the functions of the pins for the lower 8 bits in port F.
PFCR1 and PFCR2 are initialized to H'FF00 and H'00AA, respectively, by a power-on reset
(excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in
software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 504 of 818
REJ09B0273-0500
Initial value:
R/W:
Bit:
15
—
R
1
14
—
R
1
13
—
R
1
12
—
R
1
PF11
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
IOR
11
0
PF10
IOR
10
0
PF9
IOR
9
0
PF8
IOR
8
0
PF7
IOR
7
0
PF6
IOR
6
0
PF5
IOR
5
0
PF4
IOR
4
0
PF3
IOR
3
0
PF2
IOR
2
0
PF1
IOR
1
0
PF0
IOR
0
0