HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 399

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available; , /4, /16, or /64.
For further information on the clock source, bit rate register settings, and baud rate, see section
13.2.8, Bit Rate Register.
13.2.6
The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized
to H'00 by a power-on reset, in hardware standby mode and software standby mode. Manual reset
does not initialize SCR.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TxI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.
Bit 1: CKS1
0
1
Bit 7: TIE
0
1
Initial value:
Serial Control Register (SCR)
R/W:
Bit:
Bit 0: CKS0
0
1
0
1
R/W
TIE
7
0
Description
Transmit-data-empty interrupt request (TxI) is disabled (initial value).
The TxI interrupt request can be cleared by reading TDRE after it has
been set to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TxI) is enabled
R/W
RIE
6
0
Description
/4
/16
/64
(initial value)
R/W
TE
5
0
Section 13 Serial Communication Interface (SCI)
R/W
RE
4
0
Rev. 5.00 Jan 06, 2006 page 377 of 818
MPIE
R/W
3
0
TEIE
R/W
2
0
REJ09B0273-0500
CKE1
R/W
1
0
CKE0
R/W
0
0