HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 429

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 13.9.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 13.11 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the
numbers in the flowchart):
1. SCI initialization: Set the TxD pin using the PFC.
2. SCI status check and transmit data write: Read the serial status register (SSR), check that the
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
Serial
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is checked and
cleared automatically.
data
Example: Sending data H'AA to receiving processor A
Figure 13.10 Communication Among Processors Using Multiprocessor Format
MPB: Multiprocessor bit
Transmitting
processor A
processor
Receiving
(ID = 01)
receiving processor address
ID-transmit cycle:
H'01
processor B
Receiving
(MPB = 1)
(ID = 02)
Serial communication line
Section 13 Serial Communication Interface (SCI)
processor specified by ID
data sent to receiving
Data-transmit cycle:
Rev. 5.00 Jan 06, 2006 page 407 of 818
processor C
Receiving
(ID = 03)
H'AA
(MPB = 0)
REJ09B0273-0500
processor D
Receiving
(ID = 04)