HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 167

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): These bits specify
increment/decrement of the DMA transfer source address. These bit specifications are ignored
when transferring data from an external device to address space in single address mode.
Bits 13 and 12—Source Address Mode 1, 0 (SM1 and SM0): These bits specify
increment/decrement of the DMA transfer source address. These bit specifications are ignored
when transferring data from an external device to address space in single address mode.
When the transfer source is specified at an indirect address, specify in source address register 3
(SAR3) the actual storage address of the data you want to transfer as the data storage address
(indirect address).
During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this
case, SAR3’s increment/decrement is fixed at +4/–4 or 0, irrespective of the transfer data size
specified by TS1 and TS0.
Bit 15: DM1
0
0
1
1
Bit 13: SM1
0
0
1
1
Bit 14: DM0
0
1
0
1
Bit 12: SM0
0
1
0
1
Description
Destination address fixed (initial value)
Destination address incremented (+1 during 8-bit transfer, +2
during 16-bit transfer, +4 during 32-bit transfer)
Destination address decremented (–1 during 8-bit transfer, –2
during 16-bit transfer, –4 during 32-bit transfer)
Setting prohibited
Description
Source address fixed (initial value)
Source address incremented (+1 during 8-bit transfer, +2
during 16-bit transfer, +4 during 32-bit transfer)
Source address decremented (–1 during 8-bit transfer, –2
during 16-bit transfer, –4 during 32-bit transfer)
Setting prohibited
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 Jan 06, 2006 page 145 of 818
REJ09B0273-0500