HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 189

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Direct Memory Access Controller (DMAC)
9.3.7
Bus Modes
Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes:
cycle steal and burst.
Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after each
one-transfer-unit (byte, word, or longword) DMAC transfer. When the next transfer request
occurs, the bus rights are obtained from the other bus master and a transfer is performed for one
transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is
repeated until the transfer end conditions are satisfied.
The cycle steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 9.12 shows an example of DMA transfer timing in the cycle steal mode.
Transfer conditions are dual address mode and DREQ level detection.
DREQ
Bus control returned to CPU
Bus cycle
CPU
CPU
CPU
DMAC DMAC
CPU DMAC DMAC CPU
CPU
Read
Write
Read
Write
Figure 9.12 DMA Transfer Timing Example in the Cycle-Steal Mode
Burst Mode: Once the bus right is obtained, the transfer is performed continuously until the
transfer end condition is satisfied. In the external request mode with low level detection of the
DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master
after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the
transfer end conditions have not been satisfied.
Figure 9.13 shows an example of DMA transfer timing in the burst mode. Transfer conditions are
single address mode and DREQ level detection.
DREQ
Bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC DMAC
DMAC
CPU
Figure 9.13 DMA Transfer Timing Example in the Burst Mode
Rev. 5.00 Jan 06, 2006 page 167 of 818
REJ09B0273-0500