HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 133

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
8.1.3
Table 8.1 shows the bus state controller pin configuration.
Table 8.1
Note: When an 8-bit bus width is selected for external space, WRL is enabled.
8.1.4
The BSC has eight registers. These registers are used to control wait states, bus width, and
interfaces with memories like ROM and SRAM, as well as refresh control. The register
configurations are listed in table 8.2.
All registers are 16 bits. All BSC registers are all initialized by a power-on reset, but are not by a
manual reset. Values are maintained in standby mode.
Signal
A21–A0
D15–D0
CS0–CS3
RD
WRH
WRL
WAIT
BREQ
BACK
When a 16-bit bus width is selected for external space, WRH and WRL are enabled.
Pin Configuration
Register Configuration
Pin Configuration
I/O
O
I/O
O
O
O
O
I
I
O
Description
Address output
16-bit data bus.
Chip select, indicating the area being accessed
Strobe that indicates the read cycle for ordinary space/multiplex I/O.
Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary
space/multiplex I/O. Also output during DRAM access.
Strobe that indicates a write cycle to the least significant byte (D7–D0) for
ordinary space/multiplex I/O. Also output during DRAM access.
Wait state request signal
Bus release request input
Bus use enable output
Rev. 5.00 Jan 06, 2006 page 111 of 818
Section 8 Bus State Controller (BSC)
REJ09B0273-0500

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