HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet
HD64F7051SFJ20V
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HD64F7051SFJ20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7050 Group, SH7050F-ZTAT 32 SH7051F-ZTAT Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH SH7050 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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The SH7050 series (SH7050, SH7051 single-chip RISC microcontroller that integrates a RISC CPU core using an original Renesas architecture with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed ...
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Rev. 5.00 Jan 06, 2006 page ...
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Main Revisions for This Edition Item Page All 2.3.3 Instruction 35 Format Table 2.9 Instruction Formats 13.2.8 Bit Rate 385 Register (BRR) 22.2 DC 655 Characteristics Table 22.2 DC Characteristics Table 22.3 656 Permitted Output Current Values Revision (See Manual ...
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Rev. 5.00 Jan 06, 2006 page ...
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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement and Pin Functions ................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1.3.3 Pin Assignments................................................................................................... 15 Section 2 CPU ...................................................................................................................... 21 2.1 Register Configuration...................................................................................................... 21 2.1.1 ...
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Notes on Using.................................................................................................................. 58 Section 5 Exception Processing 5.1 Overview........................................................................................................................... 61 5.1.1 Types of Exception Processing and Priority ........................................................ 61 5.1.2 Exception Processing Operations......................................................................... 62 5.1.3 Exception Processing Vector Table ..................................................................... 63 5.2 Resets ................................................................................................................................ 65 5.2.1 Power-On Reset ...
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Interrupt Exception Vectors and Priority Rankings ............................................. 79 6.3 Description of Registers.................................................................................................... 84 6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) .................................................. 84 6.3.2 Interrupt Control Register (ICR).......................................................................... 86 6.3.3 IRQ Status Register (ISR).................................................................................... 87 6.4 Interrupt Operation............................................................................................................ 89 6.4.1 Interrupt ...
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Register Configuration......................................................................................... 111 8.1.5 Address Map ........................................................................................................ 112 8.2 Description of Registers.................................................................................................... 115 8.2.1 Bus Control Register 1 (BCR1) ........................................................................... 115 8.2.2 Bus Control Register 2 (BCR2) ........................................................................... 116 8.2.3 Wait Control Register 1 (WCR1)......................................................................... 119 8.2.4 Wait Control ...
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Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 169 9.3.11 Source Address Reload Function ......................................................................... 186 9.3.12 DMA Transfer Ending Conditions....................................................................... 188 9.3.13 DMAC Access from CPU.................................................................................... 189 9.4 Examples of Use ............................................................................................................... 189 9.4.1 Example of ...
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Duty Registers (DTR) .......................................................................................... 282 10.3 Operation .......................................................................................................................... 283 10.3.1 Overview.............................................................................................................. 283 10.3.2 Free-Running Count Operation and Cyclic Count Operation .............................. 285 10.3.3 Output Compare-Match Function ........................................................................ 286 10.3.4 Input Capture Function ........................................................................................ 288 10.3.5 One-Shot Pulse Function ..................................................................................... ...
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Overview.............................................................................................................. 349 11.3.2 Advanced Pulse Controller Output Operation ..................................................... 350 11.4 Usage Notes ...................................................................................................................... 353 Section 12 Watchdog Timer (WDT) 12.1 Overview........................................................................................................................... 355 12.1.1 Features................................................................................................................ 355 12.1.2 Block Diagram ..................................................................................................... 356 12.1.3 Pin Configuration................................................................................................. 356 12.1.4 Register Configuration......................................................................................... 357 ...
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Serial Status Register (SSR) ................................................................................ 380 13.2.8 Bit Rate Register (BRR) ...................................................................................... 384 13.3 Operation .......................................................................................................................... 394 13.3.1 Overview.............................................................................................................. 394 13.3.2 Operation in Asynchronous Mode ....................................................................... 396 13.3.3 Multiprocessor Communication........................................................................... 406 13.3.4 Clock Synchronous Operation ............................................................................. 414 13.4 SCI ...
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ADEND Output Pin ............................................................................................. 455 14.5 Interrupt Sources and DMA Transfer Requests ................................................................ 456 14.6 Usage Notes ...................................................................................................................... 456 Section 15 Compare Match Timer (CMT) 15.1 Overview........................................................................................................................... 459 15.1.1 Features................................................................................................................ 459 15.1.2 Block Diagram ..................................................................................................... 460 15.1.3 Register Configuration......................................................................................... ...
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Port F Control Registers 1 and 2 (PFCR1, PFCR2) ............................................. 504 16.3.13 Port G IO Register (PGIOR) ................................................................................ 510 16.3.14 Port G Control Registers 1 and 2 (PGCR1, PGCR2) ........................................... 510 16.3.15 CK Control Register (CKCR) .............................................................................. 516 Section ...
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Block Configuration ............................................................................................ 542 18.3 Pin Configuration.............................................................................................................. 542 18.4 Register Configuration...................................................................................................... 543 18.5 Register Descriptions ........................................................................................................ 544 18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 544 18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 547 18.5.3 Erase Block Register 1 (EBR1) ...
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Flash Memory Emulation in RAM ...................................................................... 590 19.2.5 Differences between Boot Mode and User Program Mode ................................. 591 19.2.6 Block Configuration ............................................................................................ 592 19.3 Pin Configuration.............................................................................................................. 593 19.4 Register Configuration...................................................................................................... 594 19.5 Register Descriptions ........................................................................................................ 595 19.5.1 Flash Memory ...
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Section 20 RAM .................................................................................................................. 639 20.1 Overview........................................................................................................................... 639 20.2 Operation .......................................................................................................................... 640 Section 21 Power-Down State 21.1 Overview........................................................................................................................... 641 21.1.1 Power-Down States.............................................................................................. 641 21.1.2 Pin Configuration................................................................................................. 643 21.1.3 Related Register ................................................................................................... 643 21.2 Register Descriptions ........................................................................................................ 644 21.2.1 Standby Control ...
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Appendix A On-Chip Supporting Module Registers A.1 Addresses .......................................................................................................................... 675 A.2 Registers............................................................................................................................ 692 A.3 Register States at Reset and in Power-Down State ........................................................... 808 Appendix B Pin States ....................................................................................................... 812 B.1 Pin States at Reset and in Power-Down, and Bus ...
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Features The SH7050 series is a single-chip RISC microcontroller that integrates a RISC CPU core using an original Renesas architecture with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed ...
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Section 1 Overview Table 1.1 SH7050 Series Features Item Features CPU Original Renesas architecture 32-bit internal architecture General register machine Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC-type instruction set Fixed 16-bit instruction length for ...
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Item Features Operating states Operating modes Single-chip mode 8/16-bit bus expanded mode (area 0 only set by mode pins) • Mode with on-chip ROM • Mode with no on-chip ROM Processing states Power-on reset state Program execution state Exception handling ...
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Section 1 Overview Item Features Bus state Supports external memory access (SRAM and ROM directly connectable) controller (BSC) 8/16-bit external data bus External address space divided into four areas, with the following parameters settable for each area: Bus size (8 ...
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Item Features Advanced timer Built-in two-stage prescaler unit (ATU) Total of 18 counters: ten free-running counters, eight down-counters Maximum 34 pulse inputs or outputs can be processed Four 32-bit input capture inputs Eight 16-bit one-shot pulse outputs Eighteen 16-bit input ...
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Section 1 Overview Item Features Large-capacity Memory on-chip memory Mask ROM Flash memory RAM Product lineup Model SH7050 SH7051 Rev. 5.00 Jan 06, 2006 page 6 of 818 REJ09B0273-0500 SH7050 128 kB — On-Chip Operating Operating ROM Voltage ...
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Block Diagram RES Port/control signals HSTBY MD3 MD2 MD1 MD0 NMI WDTOVF CK EXTAL Clock pulse XTAL generator PLLV CC PLLV SS PLLCAP ref ...
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Section 1 Overview 1.3 Pin Arrangement and Pin Functions 1.3.1 Pin Arrangement 1 PG9/TIOD3 PG10/TIOA4 2 3 PG11/TIOB4 4 PG12/TIOC4 5 PG13/TIOD4 6 PG14/IRQ4/TIOA5 PG15/IRQ5/TIOB5 8 9 PB0/TO6 10 PB1/TO7 11 PB2/TO8 12 PB3/TO9 ...
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Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Type Symbol Pin No. Power supply V 13, 21, 29, CC 37, 47, 55, 72, 79, 89, 97, 105, 113, 130, 158 V 7, 15, 23, SS ...
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Section 1 Overview Type Symbol Pin No. Clock EXTAL 110 XTAL 108 CK 125 RES System 126 control WDTOVF 51 BREQ 135 BACK 134 Operating MD0 to 120, 119, mode control MD3 111, 109 HSTBY 124 Interrupts NMI 112 IRQ0 ...
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Type Symbol Pin No. IRQOUT Interrupts 159 Address bus A0–A21 17–20, 22, 24–28, 30, 32–36, 38, 40–44 Data bus D0–D15 85–88, 90, 92–96, 98, 100–104 CS0–CS3 Bus control 52–54, 133 RD 50 WRH 46 WRL 45 WAIT 48 DREQ0– Direct ...
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Section 1 Overview Type Symbol Pin No. Advanced TCLKA 14 timer unit TCLKB 16 (ATU) TIA0 76 TIB0 77 TIC0 78 TID0 80 TIOA1 66 TIOB1 67 TIOC1 68 TIOD1 69 TIOE1 71 TIOF1 73 TIOA2 74 TIOB2 75 TIOA3 ...
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Type Symbol Pin No. Advanced TOA10 56 timer unit TOB10 58 (ATU) TOC10 59 TOD10 60 TOE10 61 TOF10 62 TOG10 63 TOH10 65 Advanced PULS0– 127–129, pulse PULS7 131–135 controller (APC) Serial TxD0– 161, 165, communication TxD2 167 interface ...
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Section 1 Overview Type Symbol Pin No. POD I/O ports 44 PA0–PA15 17–20, 22, 24–28, 30, 32–36 PB0–PB11 9–12, 14, 16, 38, 40–44 PC0–PC14 45, 46, 48, 50, 52–54, 56, 58–63, 65 PD0–PD15 85–88, 90, 92–96, 98, 100–104 PE0–PE14 66–69, ...
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Pin Assignments Table 1.3 Pin Assignments Pin No. MCU Mode 1 PG9/TIOD3 2 PG10/TIOA4 3 PG11/TIOB4 4 PG12/TIOC4 5 PG13/TIOD4 6 PG14/IRQ4/TIOA5 PG15/IRQ5/TIOB5 9 PB0/TO6 10 PB1/TO7 11 PB2/TO8 12 PB3/TO9 ...
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Section 1 Overview Pin No. MCU Mode 30 PA10/A10 PA11/A11 33 PA12/A12 34 PA13/A13 35 PA14/A14 36 PA15/A15 PB6/A16 PB7/A17 41 PB8/A18 42 PB9/A19 43 PB10/A20 44 PB11/A21/POD ...
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Pin No. MCU Mode 62 PC12/TOF10/DRAK1 63 PC13/TOG10 PC14/TOH10 66 PE0/TIOA1 67 PE1/TIOB1 68 PE2/TIOC1 69 PE3/TIOD1 PE4/TIOE1 PE5/TIOF1 74 PE6/TIOA2 75 PE7/TIOB2 76 PE8/TIA0 77 PE9/TIB0 78 ...
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Section 1 Overview Pin No. MCU Mode 94 PD7/D7 95 PD8/D8 96 PD9/ PD10/D10 100 PD11/D11 101 PD12/D12 102 PD13/D13 103 PD14/D14 104 PD15/D15 105 V CC 106 PF0/IRQ0 107 V SS 108 ...
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Pin No. MCU Mode RES 126 127 PF4/DACK1/PULS0 128 PF5/DREQ1/PULS1 129 PF6/DACK0/PULS2 130 V CC 131 PF7/DREQ0/PULS3 132 PF8/SCK2/PULS4 133 PF9/CS3/IRQ7/PULS5 134 PF10/BACK/PULS6 135 PF11/BREQ/PULS7 136 V SS 137 PH0/AN0 138 PH1/AN1 139 PH2/AN2 140 PH3/AN3 141 PH4/AN4 142 AV ...
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Section 1 Overview Pin No. MCU Mode 158 V CC 159 PG0/ADTRG/IRQOUT 160 PG1/SCK0 161 PG2/TxD0 162 PG3/RxD0 163 PG4/SCK1 164 V SS 165 PG5/TxD1 166 PG6/RxD1 167 PG7/TxD2 168 PG8/RxD2 Note: * Mask ROM version Rev. 5.00 Jan 06, ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for data ...
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Section 2 CPU 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base ...
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System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and ...
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Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when ...
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Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, ...
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Section 2 CPU Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). There are two types of conditional branch instructions: delayed branch instructions ...
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Immediate Data: Byte (8 bit) immediate data resides in instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using ...
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Section 2 CPU 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre- existing displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register ...
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Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Direct register Rn addressing Indirect register @Rn addressing Post-increment @Rn+ indirect register addressing Pre-decrement @–Rn indirect register ...
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Section 2 CPU Addressing Instruction Mode Format Indirect register @(disp:4, addressing with Rn) displacement Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register addressing Indirect GBR @(disp:8, addressing with GBR) displacement Rev. 5.00 Jan 06, ...
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Addressing Instruction Mode Format Indirect indexed @(R0, GBR addressing GBR) Indirect PC @(disp:8, addressing with PC) displacement Effective Addresses Calculation The effective address is the GBR value plus the R0. GBR + R0 The effective address is the PC value ...
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Section 2 CPU Addressing Instruction Mode Format PC relative disp:8 addressing disp:12 Rn Immediate #imm:8 addressing #imm:8 #imm:8 Rev. 5.00 Jan 06, 2006 page 32 of 818 REJ09B0273-0500 Effective Addresses Calculation The effective address is the PC value sign-extended with ...
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Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: xxxx: Instruction code mmmm: Source register nnnn: ...
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Section 2 CPU Instruction Formats nm format 15 xxxx xxxx nnnn mmmm md format 15 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx dddd nnnn mmmm Rev. 5.00 Jan 06, 2006 page 34 ...
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Instruction Formats d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx format 15 xxxx ...
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Section 2 CPU 2.4 Instruction Set by Classification Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operations ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS ...
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Operation Classification Types Code Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR RTS Function Logical AND Bit ...
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Section 2 CPU Operation Classification Types Code System 11 CLRMAC control CLRT LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and ...
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Table 2.11 Instruction Code Format Item Format Instruction OP.Sz SRC,DEST Instruction MSB LSB code Operation , (xx) M/Q/T & <<n >>n Execution — cycles T bit — Notes: 1. Depending on the operand size, displacement is scaled ...
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Section 2 CPU Table 2.12 Data Transfer Instructions Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L ...
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Instruction MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) 11000000dddddddd R0 MOV.W R0,@(disp,GBR) 11000001dddddddd R0 MOV.L R0,@(disp,GBR) 11000010dddddddd R0 MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) MOV.W @(disp,GBR),R0 11000101dddddddd (disp 2 + GBR) MOV.L @(disp,GBR),R0 11000110dddddddd (disp ...
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Section 2 CPU Table 2.13 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn ...
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Instruction Instruction Code DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG ...
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Section 2 CPU Instruction Instruction Code SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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Section 2 CPU Table 2.16 Branch Instructions Instruction Instruction Code 10001011dddddddd disp BF label 10001111dddddddd Delayed branch disp BF/S label 10001001dddddddd disp label 10001101dddddddd ...
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Table 2.17 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L ...
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Section 2 CPU Instruction Instruction Code STS.L MACH,@–Rn 0100nnnn00000010 STS.L MACL,@–Rn 0100nnnn00010010 STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. ...
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From any state when RES = 0 When an interrupt source or DMA address error occurs Bus request cleared Bus release state Bus request generated Bus request Bus request cleared generated SBY bit cleared for SLEEP instruction Sleep mode Power-down ...
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Section 2 CPU Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset results. When the RES pin is high and MRES is low, a manual reset will occur. Exception Processing ...
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Section 3 Operating Modes 3.1 Operating Mode Selection The SH7050 series has five operating modes that are selected by pins MD3 to MD0 and FWE. The mode setting pins should not be changed during operation of the SH7050 series, and ...
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Section 3 Operating Modes Rev. 5.00 Jan 06, 2006 page 52 of 818 REJ09B0273-0500 ...
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Section 4 Clock Pulse Generator (CPG) 4.1 Overview The clock pulse generator (CPG) supplies clock pulses inside the SH7050 series chip and to external devices. The SH7050 series CPG consists of an oscillator circuit and a PLL multiplier circuit. There ...
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Section 4 Clock Pulse Generator (CPG) 4.1.1 Block Diagram A block diagram of the clock pulse generator is shown in figure 4.1. EXTAL XTAL PLLV CC PLLV SS PLLCAP MD3 MD2 CK (system clock) Figure 4.1 Block Diagram of the ...
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Pin Configuration The pins relating to the clock pulse generator are shown in table 4.1. Table 4.1 CPG Pins Pin Name Abbreviation External clock EXTAL Crystal XTAL System clock CK Mode setting MD3 Mode setting MD2 PLL power supply ...
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Section 4 Clock Pulse Generator (CPG) The MD3 and MD2 pins should not be changed while the chip is operating, as normal operation will not be possible in this case. 4.3 Clock Source Clock pulses can be supplied from a ...
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Crystal Oscillator: Figure 4.3 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 4.4. EXTAL Figure 4.3 Crystal Oscillator Equivalent Circuit Table 4.4 Crystal Oscillator Parameters (Recommended Values) Parameter Rs max ...
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Section 4 Clock Pulse Generator (CPG) 4.4 Notes on Using Notes on Board Design: When connecting a crystal oscillator, observe the following precautions: To prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator ...
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R1 PLLCAP PLLV CC C PLLV Figure 4.6 Points for Caution in PLL Power Supply Connection PLLV SS PLLCAP PLLV CC EXTAL MD3 XTAL V SS Figure 4.7 Actual Example of Board Design Section ...
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Section 4 Clock Pulse Generator (CPG) Rev. 5.00 Jan 06, 2006 page 60 of 818 REJ09B0273-0500 ...
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Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur ...
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Section 5 Exception Processing 5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and the Start of Exception Processing Exception Source ...
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Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the ...
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Section 5 Exception Processing Exception Sources Interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 On-chip peripheral module * Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, ...
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Resets 5.2.1 Power-On Reset When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling ...
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Section 5 Exception Processing 5.3 Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.5. Table 5.5 Bus Cycles and Address Errors Bus Cycle Bus Type Master ...
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Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status ...
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Section 5 Exception Processing 5.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of ...
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Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.8. Table 5.8 Types of Exceptions Triggered by Instructions ...
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Section 5 Exception Processing 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception ...
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When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction sometimes not accepted immediately but stored instead, as shown in table 5.9. When this ...
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Section 5 Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.10. Table 5.10 Types of Stack Status After Exception Processing Ends Types Address error Trap ...
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Notes on Use 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed during exception processing. ...
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Section 5 Exception Processing Rev. 5.00 Jan 06, 2006 page 74 of 818 REJ09B0273-0500 ...
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Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by ...
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Section 6 Interrupt Controller (INTC) 6.1.2 Block Diagram Figure 6 block diagram of the INTC. IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 (Interrupt request) UBC (Interrupt request) DMAC (Interrupt request) ATU (Interrupt request) CMT (Interrupt ...
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Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin 6.1.4 Register Configuration The INTC has the 10 registers shown in table 6.2. ...
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Section 6 Interrupt Controller (INTC) 6.2 Interrupt Sources There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest ...
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In IRQ interrupt exception processing, the interrupt mask bits (I3–I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. 6.2.4 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by ...
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Section 6 Interrupt Controller (INTC) more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3. Table 6.3 Interrupt Exception Processing Vectors and Priorities Vector Interrupt ...
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Vector Interrupt Source No. ATU0 ATU01 ITV 80 ATU02 ICI0A 84 ICI0B 85 ICI0C 86 ICI0D 87 ATU03 OVIO 88 ATU1 ATU11 IMI1A 92 IMI1B 93 IMI1C 94 ATU12 IMI1D 96 IMI1E 97 IMI1F 98 ATU13 OV11 100 ATU2 IMI2A ...
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Section 6 Interrupt Controller (INTC) Vector Interrupt Source No. ATU3 ATU31 IMI3A 108 IMI3B 109 IMI3C 110 IMI3D 111 ATU32 OV13 112 ATU4 ATU41 IMI4A 116 IMI4B 117 IMI4C 118 IMI4D 119 ATU42 OV14 120 ATU5 IMI5A 124 IMI5B 125 ...
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Vector Interrupt Source No. ATU10 ATU101 OSI10A 132 OSI10B 133 OSI10C 134 ATU102 OSI10D 136 OSI10E 137 OSI10F 138 ATU103 OSI10G 140 OSI10H 141 CMT0 CMTI0 144 A/D0 ADI0 145 CMT1 CMT11 148 A/D1 ADI1 149 SCI0 ERI0 152 RXI0 ...
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Section 6 Interrupt Controller (INTC) Vector Interrupt Source No. SCI1 ERI1 156 RXI1 157 TXI1 158 TEI1 159 SCI2 ERI2 160 RXI2 161 TXI2 162 TEI2 163 WDT ITI 164 6.3 Description of Registers 6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) ...
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Bit: 15 Initial value: 0 R/W: R/W Bit: 7 Initial value: 0 R/W: R/W Table 6.4 Interrupt Request Sources and IPRA–IPRH Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority ...
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Section 6 Interrupt Controller (INTC) 6.3.2 Interrupt Control Register (ICR) The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 –IRQ7 and indicates the input signal level to ...
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Bits 7 to 0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7 interrupt request detection mode. Bits 7-0: IRQ0S–IRQ7S Description 0 Interrupt request is detected on low level of IRQ input (initial value) 1 Interrupt request is detected on falling ...
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Section 6 Interrupt Controller (INTC) Bits 7 to 0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt request status. Bits 7-0: IRQ0F–IRQ7F Detection Setting 0 Level detection Edge detection 1 Level detection Edge detection level IRQ pin detection edge detection ...
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Interrupt Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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Section 6 Interrupt Controller (INTC) Program execution state No Interrupt? Yes No NMI? Yes User break? IRQOUT = low level* 1 Save SR to stack Save PC to stack Copy accept-interrupt level IRQOUT = high level* ...
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Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 4n Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always be certain that ...
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Section 6 Interrupt Controller (INTC) 6.5 Interrupt Response Time Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of ...
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Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation ...
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Section 6 Interrupt Controller (INTC) interrupt source Interrupt request flag (generated by DMAC) clear Figure 6.6 Block Diagram of Interrupt Controller 6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources 1. Either do not select the DMAC as a ...
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Section 7 User Break Controller (UBC) 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus ...
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Section 7 User Break Controller (UBC) 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the UBC. Module bus UBBR UBAMRH UBAMRL Break condition comparator User break interrupt generating circuit UBARH, UBARL: User break address registers H, L UBAMRH, ...
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Register Configuration The UBC has the five registers shown in table 7.1. Break conditions are established using these registers. Table 7.1 Register Configuration Name User break address register H User break address register L User break address mask register ...
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Section 7 User Break Controller (UBC) UBARL: Bit: 15 UBARL UBA15 Initial value: 0 R/W: R/W Bit: 7 UBARL UBA7 Initial value: 0 R/W: R/W The user break address register (UBAR) consists of user break address register H (UBARH) and ...
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UBAMRL: Bit: 15 UBAMRL UBM15 Initial value: 0 R/W: R/W Bit: 7 UBAMRL UBM7 Initial value: 0 R/W: R/W The user break address mask register (UBAMR) consists of user break address mask register H (UBAMRH) and user break address mask ...
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Section 7 User Break Controller (UBC) 7.2.3 User Break Bus Cycle Register (UBBR) Bit: 15 — Initial value: 0 R/W: R Bit: 7 CP1 Initial value: 0 R/W: R/W User break bus cycle register (UBBR 16-bit readable/writable register ...
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Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to break on instruction fetch and/or data access cycles. Bit 5: ID1 Bit 4: ID0 Bits 3 and 2—Read/Write Select (RW1, ...
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Section 7 User Break Controller (UBC) 7.3 Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the ...
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UBARH/UBARL Internal address bits 31–0 CP1 CP0 CPU cycle DMA cycle ID1 ID0 Instruction fetch Data access RW1 RW0 Read cycle Write cycle SZ1 SZ0 Byte size Word size Longword size Figure 7.2 Break Condition Judgment Method Section 7 User ...
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Section 7 User Break Controller (UBC) 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in 1 bus cycle. Therefore, 2 instructions can be retrieved in 1 bus cycle ...
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Use Examples 7.4.1 Break on CPU Instruction Fetch Cycle 1. Register settings: UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 Conditions set: Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) A user ...
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Section 7 User Break Controller (UBC) 7.4.2 Break on CPU Data Access Cycle 1. Register settings: UBARH = H'0012 UBARL = H'3456 UBBR = H'006A Conditions set: Address: H'00123456 Bus cycle: CPU, data access, write, word A user break interrupt ...
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Cautions on Use 7.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory break condition is set on the second of these two instructions but the contents of the UBC break condition registers are ...
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Section 7 User Break Controller (UBC) 7.5.3 Contention between User Break and Exception Handling If a user break is set for the fetch of a particular instruction, and exception handling with higher priority than a user break is in contention ...
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Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM, and ROM to be linked directly to the LSI ...
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Section 8 Bus State Controller (BSC) 8.1.2 Block Diagram Figure 8.1 shows the BSC block diagram. control unit WAIT control unit CS0–CS3 control unit RD control unit WRH, WRL WCR1: Wait control register 1 WCR2: Wait control register 2 RAMER: ...
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Pin Configuration Table 8.1 shows the bus state controller pin configuration. Table 8.1 Pin Configuration Signal I/O Description A21–A0 O Address output D15–D0 I/O 16-bit data bus. CS0–CS3 O Chip select, indicating the area being accessed RD O Strobe ...
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Section 8 Bus State Controller (BSC) Table 8.2 Register Configuration Name Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 RAM emulation register Notes: 1. When using a longword access to ...
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Table 8.3 and table 8.4 show address map. Table 8.3 Address Map (128 kB ROM/6 kB RAM Version) • On-chip ROM effective mode Address H'0000 0000 to H'0001 FFFF H'0002 0000 to H'001F FFFF H'0020 0000 to H'003F FFFF H'0040 ...
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Section 8 Bus State Controller (BSC) Table 8.4 Address Map (256 kB ROM/10 kB RAM Version) • On-chip ROM effective mode Address H'0000 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'003F FFFF H'0040 0000 to ...
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Description of Registers 8.2.1 Bus Control Register 1 (BCR1) Bit: 15 — Initial value: 0 R/W: R Bit: 7 — Initial value: 0 R/W: R BCR1 is a 16-bit read/write register that specifies the bus size of the CS ...
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Section 8 Bus State Controller (BSC) Bit 2: A2SZ Description 0 Byte (8 bit) size 1 Word (16 bit) size (initial value) Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size setting specifies byte (8-bit) ...
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Bits 15–8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one different CS area after a read. Idles are used to prevent data ...
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Section 8 Bus State Controller (BSC) Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when doing consecutive accesses of ...
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Bit 3: SW3 Description No CS3 space CS assert extension 0 CS3 space CS assert extension (initial value) 1 Bit 2: SW2 Description No CS2 space CS assert extension 0 CS2 space CS assert extension (initial value) 1 Bit 1: ...
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Section 8 Bus State Controller (BSC) Bit 15: Bit 14: Bit 13: W33 W32 W31 Bits 11–8—CS2 Space Wait Specification (W23, W22, W21, W20): Specifies the number of waits for CS2 ...
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Wait Control Register 2 (WCR2) Bit: 15 — Initial value: 0 R/W: R Bit: 7 — Initial value: 0 R/W: R WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space and CS ...
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Section 8 Bus State Controller (BSC) 8.2.5 RAM Emulation Register (RAMER) Bit: 15 — Initial value: 0 R/W: R Bit: 7 — Initial value: 0 R/W: R The RAM emulation register (RAMER 16-bit readable/writable register that selects the ...
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Table 8.5 RAM Area Setting Method (128 kB ROM/6 kB RAM Version) RAM Area H'FFFF E800 to H'FFFF EBFF H'0001 F000 to H'0001 F3FF H'0001 F400 to H'0001 F7FF H'0001 F800 to H'0001 FBFF H'0001 FC00 to H'0001 FFFF *: ...
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Section 8 Bus State Controller (BSC) 8.3 Accessing Ordinary Space A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 8.3.1 Basic Timing Figure 8.3 shows the basic timing of ordinary space ...
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Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR settings (figure 8.4). CK Address CSn RD Read Data WRx Write Data Figure 8.4 Wait Timing of Ordinary Space ...
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Section 8 Bus State Controller (BSC) When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise ...
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CS Assert Period Extension 8.3.3 Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of ...
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Section 8 Bus State Controller (BSC) 8.4 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a ...
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Address CSn CSm RD WRx Data CSn space read Figure 8.7 Idle Cycle Insertion Example IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or ...
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Section 8 Bus State Controller (BSC) 8.4.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of the ...
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Bus Arbitration The SH7050 series has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device. It also has two internal bus masters, the CPU and the ...
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Section 8 Bus State Controller (BSC) 8.6 Memory Connection Examples Figures 8.10–8.13 show examples of the memory connections. Figure 8.10 8-Bit Data Bus Width ROM Connection Figure 8.11 16-Bit Data Bus Width ROM Connection Rev. 5.00 Jan 06, 2006 page ...
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SH705x CSn RD A0–A16 WRL D0–D7 Figure 8.12 8-Bit Data Bus Width SRAM Connection SH705x CSn RD A0 A1ÐA17 WRH D8–D15 WRL D0–D7 Figure 8.13 16-Bit Data Bus Width SRAM Connection Section 8 Bus State Controller (BSC) 128k 8 bit ...
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Section 8 Bus State Controller (BSC) Rev. 5.00 Jan 06, 2006 page 134 of 818 REJ09B0273-0500 ...
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Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SH7050 series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped ...
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Section 9 Direct Memory Access Controller (DMAC) Channel 3: Dual address mode only. Direct address transfer mode and indirect address transfer mode selectable. Reload function: Enables automatic reloading of the value set in the first source address register every fourth ...
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Block Diagram Figure 9 block diagram of the DMAC. On-chip ROM On-chip RAM On-chip peripheral module DREQ0, DREQ1 ATU SCI0–SCI2 A/D converter 0, 1 DEIn DACK0, DACK1 DRAK0, DRAK1 External ROM External RAM External I/O (memory mapped) ...
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Section 9 Direct Memory Access Controller (DMAC) 9.1.3 Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 DMAC Pin Configuration Channel Name 0 DMA transfer request DMA transfer request acknowledge DREQ0 acceptance confirmation 1 DMA transfer request DMA transfer ...
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Table 9.2 DMAC Registers Chan- nel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA ...
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Section 9 Direct Memory Access Controller (DMAC) Chan- nel Name 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Shared DMA operation register Notes: Registers are accessed in ...
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Bit: 31 Initial value: — R/W: R/W Bit: 23 Initial value: — R/W: R/W 9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer. ...
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Section 9 Direct Memory Access Controller (DMAC) 9.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count). Specifying ...
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DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3 32-bit read/write register where the operation and transmission of each channel is designated. Bits 31–21 and bit 7 should always read 0. The written value ...
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Section 9 Direct Memory Access Controller (DMAC) Bit 19—Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 for CHCR0, CHCR1, ...
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Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): These bits specify increment/decrement of the DMA transfer source address. These bit specifications are ignored when transferring data from an external device to address space in single address mode. ...
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Section 9 Direct Memory Access Controller (DMAC) Bits 11–8—Resource Select 3–0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 ...
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Bit 5—Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 5: TM Description 0 Cycle steal mode (initial value) 1 Burst mode Bits 4 and 3—Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer. Bit ...
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Section 9 Direct Memory Access Controller (DMAC) Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE Description 0 Operation of the corresponding channel disabled (initial value) 1 Operation of the corresponding channel enabled Transfer mode ...
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Bits 9–8—Priority Mode 1 and 0 (PR1 and PR0): These bits determine the priority level of channels for execution when transfer requests are made for several channels simultaneously. Bit 9: PR1 Bit 8: PR0 ...
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Section 9 Direct Memory Access Controller (DMAC) Even when the DME bit is set, when the TE bit of the CHCR its DE bit is 0, transfer is disabled in the case of an NMI of the ...
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Figure 9 flowchart of this procedure. Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE Yes Transfer request occurs Yes Transfer (1 transfer unit); DMATCR – 1 ...
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Section 9 Direct Memory Access Controller (DMAC) 9.3.2 DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither ...
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On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal on-chip peripheral module. As indicated in table 9.4, there are ten transfer request signals: five from the multifunction ...
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Section 9 Direct Memory Access Controller (DMAC) Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits DMAC Transfer RS3 RS2 RS1 RS0 Request Source ATU 1 ATU SCI0 transmit ...
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In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt enable bit for each module, and output an interrupt signal. When an on-chip peripheral module’s interrupt request signal is used as a DMA transfer ...
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Section 9 Direct Memory Access Controller (DMAC) Transfer on channel 0 Initial priority setting Priority after transfer Transfer on channel 1 Initial priority setting Priority after transfer Transfer on channel 2 Initial priority setting Priority after transfer Priority after transfer ...
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Figure 9.4 shows the example of changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The DMAC operates in the following ...
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Section 9 Direct Memory Access Controller (DMAC) 9.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode, in which either the transfer source or destination is accessed using an ...
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Address Modes Single Address Mode: In the single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACK signal while the other is accessed by an address. In this mode, the DMAC ...
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Section 9 Direct Memory Access Controller (DMAC) CK A21–A0 CSn D15–D0 DACK WRH WRL a. External device with DACK to external memory space CK A21–A0 CSn D15–D0 RD DACK b. External memory space to external device with DACK Figure 9.6 ...
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Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the transfer data ...
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Section 9 Direct Memory Access Controller (DMAC) CK A21–A0 CSn D15–D0 RD WRH, WRL DACK Note: Transfer between external memories with DACK are output during read cycle. Figure 9.8 Direct Address Transfer Timing in Dual Address Mode Rev. 5.00 Jan ...
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Indirect Address Transfer Mode: In this mode the memory address storing the data you actually want to transfer is specified in DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address ...
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Section 9 Direct Memory Access Controller (DMAC) 2nd bus cycle DMAC SAR3 DAR3 Temporary buffer Data buffer The SAR value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the ...
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External memory space External memory space (External memory space has 16-bit width) CK Transfer A21–A0 source address (H) CSn Indirect D15–D0 address (H) Internal Transfer source address address bus Internal Transfer source address data bus DMAC indirect address buffer DMAC ...
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Section 9 Direct Memory Access Controller (DMAC) Figure 9.11 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle ...
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Bus Modes Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes: cycle steal and burst. Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after ...
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Section 9 Direct Memory Access Controller (DMAC) 9.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 9.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 9.6 Relationship of Request Modes ...
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Bus Mode and Channel Priority Order When a given channel is transferring in burst mode, and a transfer request is issued to channel 0, which has a higher priority ranking, transfer on channel 0 begins immediately. If the priority ...
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Section 9 Direct Memory Access Controller (DMAC) continuously from the second bus cycle. The dummy cycle is not counted in the number of transfer cycles, so there is no need to recognize the dummy cycle when setting the TCR. DREQ ...
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Figure 9.15 Cycle Steal, Dual Address and Level Detection (Fastest Operation) Section 9 Direct Memory Access Controller (DMAC) Rev. 5.00 Jan 06, 2006 page 171 of 818 REJ09B0273-0500 ...
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Section 9 Direct Memory Access Controller (DMAC) Figure 9.16 Cycle Steal, Dual Address and Level Detection (Normal Operation) Rev. 5.00 Jan 06, 2006 page 172 of 818 REJ09B0273-0500 ...
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Figures 9.17 and 9.18 show cycle steal mode and single address mode. In this case, transfer begins at earliest three cycles after the first DREQ sampling. The second sampling begins from the start of the transfer one bus cycle before ...
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Section 9 Direct Memory Access Controller (DMAC) Figure 9.17 Cycle Steal, Single Address and Level Detection (Fastest Operation) Rev. 5.00 Jan 06, 2006 page 174 of 818 REJ09B0273-0500 ...
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Figure 9.18 Cycle Steal, Single Address and Level Detection (Normal Operation) Section 9 Direct Memory Access Controller (DMAC) Rev. 5.00 Jan 06, 2006 page 175 of 818 REJ09B0273-0500 ...
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Section 9 Direct Memory Access Controller (DMAC) Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with dual address and level detection is virtually the same as that of cycle steal mode. For example, DMAC transfer ...
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Figure 9.19 Burst Mode, Dual Address and Level Detection (Fastest Operation) Section 9 Direct Memory Access Controller (DMAC) Rev. 5.00 Jan 06, 2006 page 177 of 818 REJ09B0273-0500 ...
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Section 9 Direct Memory Access Controller (DMAC) Figure 9.20 Burst Mode, Dual Address and Level Detection (Normal Operation) Rev. 5.00 Jan 06, 2006 page 178 of 818 REJ09B0273-0500 ...