HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 263

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Bit 2—Input Capture/Compare-Match Flag (IMF1C): Status flag that indicates GR1C input
capture or compare-match.
Bit 1—Input Capture/Compare-Match Flag (IMF1B): Status flag that indicates GR1B input
capture or compare-match.
Bit 0—Input Capture/Compare-Match Flag (IMF1A): Status flag that indicates GR1A input
capture or compare-match.
Bit 2:
IMF1C
0
1
Bit 1:
IMF1B
0
1
Bit 0:
IMF1A
0
1
Description
[Clearing condition]
When IMF1C is read while set to 1, then 0 is written in IMF1C
[Setting conditions]
Description
[Clearing condition]
When IMF1B is read while set to 1, then 0 is written in IMF1B
[Setting conditions]
Description
[Clearing condition]
When IMF1A is read while set to 1, then 0 is written in IMF1A
[Setting conditions]
When the TCNT1 value is transferred to GR1C by an input capture signal while
GR1C is functioning as an input capture register
When TCNT1 = GR1C while GR1C is functioning as an output compare register
When the TCNT1 value is transferred to GR1B by an input capture signal while
GR1B is functioning as an input capture register
When TCNT1 = GR1B while GR1B is functioning as an output compare register
When the TCNT1 value is transferred to GR1A by an input capture signal while
GR1A is functioning as an input capture register
When TCNT1 = GR1A while GR1A is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 241 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500
(Initial value)
(Initial value)
(Initial value)

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