HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 301

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When the one-shot pulse function is used, DCNT starts counting down when the corresponding
DSTR bit is set to 1 by the user program after the DCNT value has been set. When the DCNT
value underflows, the corresponding DSTR bit and DCNT are automatically cleared to 0, and the
count is stopped. At the same time, the corresponding channel 10 timer status register F (TSRF)
status flag is set to 1.
When the offset one-shot pulse function is used, on compare-match with a channel 1 or 2 general
register (GR) when the corresponding timer connection register (TCNR) bit is 1, the
corresponding down-count start register (DSTR) bit is automatically set to 1 and the down-count
is started. When the DCNT value underflows, the corresponding DSTR bit and DCNT are
automatically cleared to 0, and the count is stopped. At the same time, the corresponding channel
10 TSRF status flag is set to 1.
The DCNT counters are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a word read or write.
The DCNT counters are initialized to H'0000 by a power-on reset, and in hardware standby mode
and software standby mode.
For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse
Function.
10.2.16 Offset Base Register (OSBR)
The offset base register (OSBR) is a 16-bit register. The ATU has one OSBR register in channel 1.
Offset Base Register (OSBR)
OSBR is a 16-bit read-only register used exclusively for input capture. OSBR uses the channel 0
ICR0A input capture register input as its trigger signal (TRG0A), and stores the TCNT1 value on
detection of the edge selected with bits 0 and 1 of TIORA.
Channel
1
Initial value:
R/W:
Bit:
Abbreviation
OSBR
31
R
0
30
R
0
29
R
0
28
R
0
Function
Dedicated input capture register with signal from channel 0
ICR0A as input trigger
27
R
0
26
R
0
25
R
0
24
R
0
23
Rev. 5.00 Jan 06, 2006 page 279 of 818
R
0
Section 10 Advanced Timer Unit (ATU)
22
R
0
21
R
0
20
R
0
19
R
0
REJ09B0273-0500
18
R
0
17
R
0
16
R
0