HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 166

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Direct Memory Access Controller (DMAC)
Bit 19—Source Address Reload (RO): Selects whether to reload the source address initial value
during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 for CHCR0,
CHCR1, and CHCR3, and cannot be modified.
Bit 19: RO
0
1
Bit 18—Request Check Level (RL): Selects whether to output DRAK notifying external device
of DREQ received, with active high or active low. This bit is valid only for CHCR0 and CHCR1.
It always reads 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 18: RL
0
1
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether to output DACK in
the data write cycle or data read cycle. In single address mode, DACK is always output
irrespective of the setting of this bit. This bit is valid only for CHCR0 and CHCR1. It always reads
as 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 17: AM
0
1
Bit 16—Acknowledge Level (AL): Specifies whether to set DACK (acknowledge) signal output
to active high or active low. This bit is valid only with CHCR0 and CHCR1. It always reads as 0
for CHCR2 and CHCR3, and cannot be modified.
Bit 16: AL
0
1
Rev. 5.00 Jan 06, 2006 page 144 of 818
REJ09B0273-0500
Description
Does not reload source address (initial value)
Reloads source address
Description
Output DRAK with active high (initial value)
Output DRAK with active low
Description
Outputs DACK during read cycle (initial value)
Outputs DACK during write cycle
Description
Active high output (initial value)
Active low output