HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 210

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Direct Memory Access Controller (DMAC)
9.3.12
The DMA transfer ending conditions vary for individual channels ending and for all channels
ending together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (TCR) is 0, or when the DE bit of the
channel’s CHCR is cleared to 0.
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the
NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or when the DME
bit in the DMAOR is cleared to 0.
Rev. 5.00 Jan 06, 2006 page 188 of 818
REJ09B0273-0500
When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's
DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt
enable) bit has been set, a DMAC interrupt (DEI) is requested of the CPU.
When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR. The TE bit is not set when this happens.
When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address
error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their
transfers. The DMAC obtains the bus rights, and if these flags are set to 1 during execution of
a transfer, DMAC halts operation when the transfer processing currently being executed ends,
and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bits
are set to 1 during a transfer, the DMA source address register (SAR), designation address
register (DAR), and transfer count register (TCR) are all updated. The TE bit is not set. To
resume the transfers after NMI interrupt or address error processing, clear the appropriate flag
bit to 0. To avoid restarting a transfer on a particular channel, clear its DE bit to 0.
When the processing of a one unit transfer is complete. In a dual address mode direct address
transfer, even if an address error occurs or the NMI flag is set during read processing, the
transfer will not be halted until after completion of the following write processing. In such a
case, SAR, DAR, and TCR values are updated. In the same manner, the transfer is not halted in
dual address mode indirect address transfers until after the final write processing has ended.
When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR aborts the
transfers on all channels. The TE bit is not set.
DMA Transfer Ending Conditions