HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 421

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for
transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart):
1. SCI initialization: Set the TxD pin using the PFC.
2. SCI status check and transmit data write: Read the serial status register (SSR), check that the
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0,
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE
to 0.
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TxI) in order to write data in TDR, the TDRE bit is
checked and cleared automatically.
then clear the TE to 0 in SCR and use the PFC to establish the TxD pin as an output port.
Figure 13.4 Sample Flowchart for SCI Initialization
Select transmit/receive format in SMR
Set TE or RE to 1 in SCR; Set RIE,
TIE, TEIE, and MPIE as necessary
Clear TE and RE bits to 0 in SCR
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
1-bit interval elapsed?
Set value to BRR
Initialize
End
Yes
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 399 of 818
No
1
2
3
4
REJ09B0273-0500

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