HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 335

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.5
10.5.1
Free-running counter 0 (TCNT0) and input capture registers 0A to 0D (ICR0A to ICR0D) are 32-
bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a read or
write (read only, in the case of ICR0A to ICR0D) is automatically divided into two 16-bit
accesses.
Figure 10.37 shows a read from TCNT0, and figure 10.38 a write to TCNT0.
When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal
data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer
register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer
register is output to the internal data bus.
When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer
register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time,
the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write.
The above method performs simultaneous reading and simultaneous writing of 32-bit data,
preventing contention with an up-count.
CPU
CPU
Internal data bus
Internal data bus
CPU Interface
Registers Requiring 32-Bit Access
H
L
interface
interface
Bus
Bus
Figure 10.37 Read from TCNT0
1st read operation
2nd read operation
L
Module data
bus
buffer register
buffer register
Internal
Internal
Rev. 5.00 Jan 06, 2006 page 313 of 818
Section 10 Advanced Timer Unit (ATU)
Module data bus
Module data
bus
REJ09B0273-0500
H
L
TCNT0H
TCNT0H
TCNT0L
TCNT0L