HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 114

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Interrupt Controller (INTC)
6.5
Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is
accepted.
Table 6.5
Item
DMAC active judgment
Compare identified inter-
rupt priority with SR mask
level
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
Interrupt
response
time
Note:
Rev. 5.00 Jan 06, 2006 page 92 of 818
REJ09B0273-0500
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* When m1 = m2 = m3 = m4 = 1
Interrupt Response Time
Interrupt Response Time
Maximum: 12 + 2 (m1 + m2 +
Minimum: 10
Total: 7 + m1 + m2 + m3
NMI, Peripheral
Module
0 or 1
2
X ( 0)
5 + m1 + m2 + m3
m3) + m4
Number of States
IRQ
1
3
8 + m1 + m2 + m3
11
12 + 2 (m1 + m2 +
m3) + m4
Notes
1 state required for interrupt
signals for which DMAC
activation is possible
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Performs the PC and SR
saves and vector address
fetch.
0.50 to 0.55 µs at 20 MHz
0.95 µs at 20 MHz *