HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 286

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Bit 2—One-Shot Pulse Interrupt Enable (OSE10C): Enables or disables interrupt requests by
OSF10C in TSR when OSF10C is set to 1.
Bit 2:
OSE10C
0
1
Bit 1—One-Shot Pulse Interrupt Enable (OSE10B): Enables or disables interrupt requests by
OSF10B in TSR when OSF10B is set to 1.
Bit 1:
OSE10B
0
1
Bit 0—One-Shot Pulse Interrupt Enable (OSE10A): Enables or disables interrupt requests by
OSF10A in TSR when OSF10A is set to 1.
Bit 0:
OSE10A
0
1
10.2.9
The interval interrupt request register (ITVRR) is an 8-bit register. The ATU has one ITVRR
register in channel 0.
ITVRR is an 8-bit readable/writable register used for channel 0 interval interrupt bit setting.
ITVRR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev. 5.00 Jan 06, 2006 page 264 of 818
REJ09B0273-0500
Initial value:
Interval Interrupt Request Register (ITVRR)
Description
OSI10C interrupt requested by OSF10C is disabled
OSI10C interrupt requested by OSF10C is enabled
Description
OSI10B interrupt requested by OSF10B is disabled
OSI10B interrupt requested by OSF10B is enabled
Description
OSI10A interrupt requested by OSF10A is disabled
OSI10A interrupt requested by OSF10A is enabled
R/W:
Bit:
ITVAD3 ITVAD2 ITVAD1 ITVAD0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
ITVE3
R/W
3
0
ITVE2
R/W
2
0
ITVE1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
ITVE0
R/W
0
0

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