HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 636

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 ROM (256 kB Version)
Rev. 5.00 Jan 06, 2006 page 614 of 818
REJ09B0273-0500
Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1(2). More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Increment
address
NG
NG
Figure 19.8 Erase/Erase-Verify Flowchart
Set block start address to verify address
H'FF dummy write to verify address
Clear ESU1(2) bit in FLMCR1(2)
Set ESU1(2) bit in FLMCR1(2)
Clear EV1(2) bit in FLMCR1(2)
Clear E1(2) bit in FLMCR1(2)
Set EV1(2) bit in FLMCR1(2)
Set E1(2) bit in FLMCR1(2)
*4
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Last address of block?
Verify data = all "1"?
erasing of all erase
Read verify data
End of erasing
Wait (200) s
Enable WDT
Set EBR1(2)
Disable WDT
Wait (10) s
Wait (10) s
Wait (10) s
Wait (20) s
Wait (5) ms
Wait (2) s
Wait (5) s
blocks?
End of
n = 1
Start
OK
OK
OK
*1
NG
*3
Start erase
Halt erase
*2
Clear EV1(2) bit in FLMCR1(2)
Clear SWE bit in FLMCR1
Erase failure
Wait (5) s
n
61?
OK
NG
n
n + 1