HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 338

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
10.5.4
The timer mode register (TMOR), prescaler register 1 (PSCR1), timer I/O control register 0
(TIOR0), the trigger selection register (TGSR), interval interrupt request register (ITVRR), timer
status register (TSR), timer interrupt enable register (TIER), and down-count start register (DSTR)
are 8-bit registers. These registers are connected to the upper 8 bits or lower 8 bits of the internal
16-bit data bus, and can be read or written a byte at a time.
Figures 10.43 and 10.44 show the operation when performing individual byte read or write
accesses to TGSR and TIOR0A.
10.6
Sample setup procedures for activating the various ATU functions are shown below.
Sample Setup Procedure for Input Capture: An example of the setup procedure for input
capture is shown in figure 10.45.
1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1).
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the
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REJ09B0273-0500
CPU
CPU
For channels 1 to 5, also select the second-stage counter clock " with the CKSEL bit in the
timer control register (TCR). When selecting an external clock, also select the external clock
edge type with the CKEG bit in TCR.
port for signal input as the input capture trigger, to ATU input capture input.
timer I/O control register (TIOR).
If necessary, an interrupt request can be sent to the CPU on input capture by making the
appropriate setting in the interrupt enable register (TIER).
Registers Requiring 8-Bit Access
Sample Setup Procedures
Only upper 8 bits used
Only lower 8 bits used
Internal data bus
Internal data bus
Figure 10.44 Byte Read/Write Access to TIORA
Figure 10.43 Byte Read/Write Access to TGSR
interface
interface
Bus
Bus
Only upper 8 bits used
Only lower 8 bits used
Module data bus
Module data bus
TIOR0A
TGSR