HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 467

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Bits 1 and 0—Channel Select 1 and 0 (CH1 and CH0): These bits, together with the SCAN bit,
select the analog input channels.
To prevent incorrect operation, ensure that the ADST bit in A/D control/status register 1
(ADCSR1) is cleared to 0 before changing the analog input channel selection.
14.2.5
A/D control register 1 (ADCR1) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR1 is initialized to H'7F by a power-on reset, and in hardware standby mode and software
standby mode.
Bit 7—Trigger Enable (TRGE): Same as TRGE in ADCR0.
Bits 6 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Bit 1:
CH3
0
1
Initial value:
A/D Control Register 1 (ADCR1)
Bit 0:
CH0
0
1
0
1
R/W:
Bit:
TRGE
R/W
7
0
AN12
AN13
AN14
AN15
Single Mode
R
6
1
(Initial value)
R
5
1
Analog Input Channels
R
4
1
Rev. 5.00 Jan 06, 2006 page 445 of 818
Scan Mode
AN12
AN12, 13
AN12–14
AN12–15
R
3
1
Section 14 A/D Converter
R
2
1
REJ09B0273-0500
R
1
1
R
0
1

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