HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 386

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 12 Watchdog Timer (WDT)
12.3.2
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer
interrupt (ITI) is generated each time the timer counter overflows. This function can be used to
generate interval timer interrupts at regular intervals (figure 12.5).
12.3.3
The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When
using the standby mode, set the WDT as described below.
Before Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop
the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby
mode while the TME bit is set to 1. Set bits CKS2 to CKS0 so that the counter overflow interval is
equal to or longer than the oscillation settling time. See section 22.3, AC Characteristics, for the
oscillation settling time.
Recovery from the Standby Mode: When an NMI request signal is received in standby mode,
the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected
by bits CKS2 to CKS0 before the standby mode was entered. When the TCNT overflows (changes
from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the
entire chip and the standby mode ends.
For details on the standby mode, see section 21, Power-Down States.
Rev. 5.00 Jan 06, 2006 page 364 of 818
REJ09B0273-0500
H'FF
H'00
ITI: Interval timer interrupt request generation
TCNT value
WT/IT = 0
Interval Timer Mode
Clearing the Standby Mode
TME = 1
Figure 12.5 Operation in the Interval Timer Mode
Overflow
ITI
Overflow
ITI
Overflow
ITI
Overflow
ITI
Time

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