HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 663

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
21.1
In the power-down state, the CPU functions are halted. This enables a great reduction in power
consumption.
21.1.1
The power-down state is effected by the following three modes:
1. Hardware standby mode
2. Software standby mode
3. Sleep mode
Table 21.1 describes the transition conditions for entering the modes from the program execution
state as well as the CPU and peripheral function status in each mode and the procedures for
canceling each mode.
A transition to hardware standby mode is made according to the input level of the RES and
HSTBY pins.
In hardware standby mode, all chip functions are halted.
This state is exited by means of a power-on reset.
A transition to software standby mode is made by means of software (a CPU instruction).
In software standby mode, all chip functions are halted.
This state is exited by means of a power-on reset or an NMI interrupt.
A transition to sleep mode is made by means of a CPU instruction.
In software standby mode, basically only the CPU is halted, and all on-chip peripheral modules
operate.
This state is exited by means of a power-on reset, interrupt, or DMA address error.
Overview
Power-Down States
Section 21 Power-Down State
Rev. 5.00 Jan 06, 2006 page 641 of 818
Section 21 Power-Down State
REJ09B0273-0500

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