HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 317

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3.9
PWM mode is set unconditionally for ATU channels 6 to 9, and also by setting 1 in the
corresponding bit (T3PWM to T5PWM) of the ATU channel 3 to 5 timer mode registers (TMDR),
enabling the counters to be used as PWM timers.
In ATU channels 6 to 9, when the free-running counter (TCNT) is started, 0 is output to the
external pin if the corresponding duty register (DTR6 to DTR9) value is 0, and 1 is output to the
external pin if the DTR6 to DTR9 value is 1. When the TCNT count matches the DTR6 to DTR9
value after the up-count is started, 0 is output to the corresponding external pin (unless 100% duty
has been set, in which case 1 is output). When the continuing TCNT up-count matches the cycle
register (CYLR) value, 1 is output to the corresponding external pin (unless 0% duty has been set,
in which case 0 is output). At the same time, the counter is cleared. 0% duty is specified by setting
DTR to H'0000, and 100% duty by setting DTR
The relationship between pins and registers is shown in table 10.4. Details of the buffer function
for ATU channels 6 to 9 are given in section 10.3.10, Buffer Function.
Channel 0
counter
value
TCNT0
Channel 1
counter
value
TCNT1
PWM Timer Function
H'FFFFFFFF
H'00000000
ICR0AH/L
Data X1
Data X2
Data Y1
Data Y2
H'FFFF
H'0000
OSBR
TIA0
Figure 10.19 Example of Twin-Capture Operation
CYLR.
Data X1
Data Y1
Rev. 5.00 Jan 06, 2006 page 295 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500
Data X2
Data Y2
Time
Time