HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 717

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial Control Register (SCR)
Bit
7
6
5
4
3
2
1, 0
Initial value:
Bit Name
Transmit interrupt
enable (TIE)
Receive interrupt enable
(RIE)
Transmit enable (TE)
Receive enable (RE)
Multiprocessor interrupt
enable (MPIE)
Transmit-end interrupt
enable (TEIE)
Clock enable 1 and 0
(CKE1, CKE0)
Bit name:
R/W:
Bit:
R/W
TIE
7
0
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
RIE
6
0
Description
Transmit-data-empty interrupt request (TXI) is disabled
Transmit-data-empty interrupt request (TXI) is enabled
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Transmitting is disabled
Transmitting is enabled
Receiving is disabled
Receiving is enabled
Multiprocessor interrupts are disabled (normal receive operation)
[Clearing conditions]
1. Clearing MPIE to 0
2. When data with MPB = 1 is received
Multiprocessor interrupts are enabled
Receive data full interrupt (RXI) and receive error interrupt (ERI) requests, and
setting of RDRF, FER, and ORER flags in SSR, are disabled until data with the
multiprocessor bit set to 1 is received.
Transmit-end interrupt requests (TEI) are disabled
Transmit-end interrupt requests (TEI) are enabled
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
R/W
TE
5
0
H'FFFF81A2 (Channel 0)
H'FFFF81B2 (Channel 1)
H'FFFF81C2 (Channel 2)
Appendix A On-Chip Supporting Module Registers
R/W
RE
Internal clock, SCK pin used as input pin (input signal
ignored) or output pin (output level undefined)
Internal clock, SCK pin used for serial clock output
Internal clock, SCK pin used for clock output
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input
External clock, SCK pin used for serial clock input
4
0
Rev. 5.00 Jan 06, 2006 page 695 of 818
MPIE
R/W
3
0
TEIE
R/W
2
0
8/16
REJ09B0273-0500
CKE1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
CKE0
R/W
0
0
SCI