AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 714
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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42.2.6.2
42.2.7
42.2.7.1
42.2.7.2
42.2.7.3
714
AT91SAM9G10
Serial Synchronous Controller (SSC)
SPI: Software Reset Must be Written Twice
SSC: Transmitter Limitations in Slave Mode
SSC: Periodic Transmission Limitations in Master Mode
SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
None.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
If TK is programmed as input and TF is programmed as output and requested to be set to
low/high during data emission, the Frame Synchro is generated one bit clock period after the
data start, one data bit is lost. This problem does not exist when generating periodic synchro.
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are AT91SAM9G10 signals, TXD is the delayed
data to connect to the device.
If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not
sent.
None.
When the SSC receiver is used with the following conditions:
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6462A–ATARM–03-Jun-09
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