AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 23

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.10
9.11
6462A–ATARM–03-Jun-09
Advanced Interrupt Controller
Debug Unit
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
• Four External Sources
• 8-level Priority Controller
• Vectoring
• Protect Mode
• Fast Forcing
• General Interrupt Mask
• Composed of four functions
• Two-pin UART
• Debug Communication Channel Support
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive
– Drives the normal interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
– Easy debugging by preventing automatic operations when protect mode is enabled
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
– Provides processor synchronization on events without triggering an interrupt
– Two-pin UART
– Debug Communication Channel (DCC) support
– Chip ID Registers
– ICE Access Prevention
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
interrupts
processor
Generator
AT91SAM9G10
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