AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 240

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 25-4. Divider and PLL Block Diagram
25.4.1
Figure 25-5. PLL Capacitors and Resistors
25.4.2
6462A–ATARM–03-Jun-09
PLL Filter
Divider and Phase Lock Loop Programming
MAINCK
The PLL requires connection to an external second-order filter through the PLLRCA and/or PLL-
RCB pin.
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
SLCK
Figure 25-5
C2
shows a schematic of these filters.
C1
R
Divider B
Divider A
DIVB
DIVA
PLLRC
GND
PLLRCB
PLLRCA
MULB
MULA
PLLBCOUNT
PLLACOUNT
PLL
Counter
Counter
PLL B
PLL A
PLL B
PLL A
OUTB
OUTA
LOCKA
LOCKB
AT91SAM9G10
PLLBCK
PLLACK
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