AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 208
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure 23-4. Read Burst with Boundary Row Access
23.5.4
6462A–ATARM–03-Jun-09
SDRAMC_A[12:0]
D[31:0]
SDWE
SDCS
SDCK
RAS
CAS
SDRAM Controller Refresh Cycles
col a
Row n
col b
Dna
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is
loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles
between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the
device is busy and the master is held by a wait signal. See
col c
Dnb
col d
Dnc
Dnd
T
RP
= 3
Row m
T
RCD
= 3
col a
CAS = 2
Figure
col b
Dma
col c
23-5.
AT91SAM9G10
Dmb
col d
Dmc
col e
Dmd
Dme
208
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