AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 641

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6462A–ATARM–03-Jun-09
can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of
LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCD-
DOTCK signal depends on the configuration. This information can be found in
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the
LCDCON2 register:
Table 38-13. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to
cause the line to be displayed on the panel.
The following timing parameters can be configured:
DISTYPE
TFT
STN Mono
STN Mono
STN Mono
STN Mono
STN Color
STN Color
STN Color
STN Color
• Always Active (used with TFT LCD Modules)
• Active only when data is available (used with STN LCD Modules)
• Vertical to Horizontal Delay (VHDLY): The delay between begin_of_line and the generation of
• Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of
• Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first
• Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is
LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to
(VHDLY+1) LCDDOTCK cycles.
LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles.
LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field
of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles.
configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2)
LCDDOTCK cycles.
f
LCDDOTCK
SCAN
Single
Single
Dual
Dual
Single
Single
Dual
Dual
=
-------------------------------- -
2
Configuration
f
LCDC_clock
×
CLKVAL
IFWIDTH
4
8
8
16
4
8
8
16
AT91SAM9G10
LCDDOTCK Period
1
4
8
8
16
2
2
4
6
Table
38-13.
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