AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 593

KIT DEV FOR SAM9G10 ARM

AT91SAM9G10-EK

Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Datasheets

Specifications of AT91SAM9G10-EK

Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
37.3.2
37.3.3
593
AT91SAM9G10
Power Management
Interrupt
To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to
assign this I/O in input PIO mode.
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL
with an accuracy of ± 0.25%.
Thus, the USB device receives two clocks from the Power Management Controller (PMC): the
master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to inter-
face with the bus USB signals (recovered 12 MHz domain).
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be
enabled before any read/write operations to the UDP registers including the UDP_TXVC
register.
The USB device interface has an interrupt line connected to the Advanced Interrupt Controller
(AIC).
Handling the USB device interrupt requires programming the AIC before configuring the UDP.
Table 37-2.
Instance
UDP
Peripheral IDs
10
ID
6462A–ATARM–03-Jun-09

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