AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 249
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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26.8
26.8.1
6462A–ATARM–03-Jun-09
Clock Switching Details
Master Clock Switching Timings
Table 26-1
from one selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock
has to be added.
Table 26-1.
Notes:
Table 26-2.
To
Main Clock
SLCK
PLL Clock
To
PLLA Clock
PLLB Clock
1. PLL designates either the PLL A or the PLL B Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
From
and
From
Clock Switching Timings (Worst Case)
Clock Switching Timings Between Two PLLs (Worst Case)
Table 26-2
PLLCOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLx Clock
Main Clock
4.5 x SLCK
4 x SLCK +
–
give the worst case timings required for the Master Clock to switch
PLLACOUNT x SLCK
2.5 x PLLA Clock +
3 x PLLB Clock +
1.5 x PLLB Clock
PLLA Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
PLLCOUNT x SLCK
AT91SAM9G10
PLLBCOUNT x SLCK
2.5 x PLL Clock +
2.5 x PLLB Clock +
3 x PLL Clock +
3 x PLL Clock +
3 x PLLA Clock +
1.5 x PLLA Clock
1 x Main Clock
4 x SLCK +
4 x SLCK +
PLL Clock
PLLB Clock
5 x SLCK
4 x SLCK +
4 x SLCK +
249
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