AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 707
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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39.9.3
Table 39-30. MCI Timings
6462A–ATARM–03-Jun-09
MCI
MCI
MCI
MCI
MCI
Symbol
1
2
3
4
5
MCI
CLK frequency at Data transfer Mode
CLK frequency at Identification Mode
CLK Low time
CLK High time
CLK Rise time
CLK Fall time
CLK Low time
CLK High time
CLK Rise time
CLK Fall time
Input hold time
Input setup time
Output change after CLK rising
Output valid before CLK rising
The PDC interface block controls all data routing between the external data bus, internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine
that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters
for the MMC/SD module (inner system) and the application (user programming).
These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card.
Figure 39-19. MCI Timing Diagram
Parameter
CMD_DAT Output
CMD_DAT Input
CLK
C= 100 pf
C= 250 pf
C= 100 pf
C= 100 pf
C= 100 pf
C= 100 pf
C= 250 pf
C= 250 pf
C= 250 pf
C= 250 pf
C = 25 pf
CLoad
MCI2
MCI4
MCI1
MCI3
MCI5
Min
10
10
50
50
3
3
5
5
Shaded areas are not valid
AT91SAM9G10
Max
400
25
20
20
10
10
50
50
Units
MHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
707
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