AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 562
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure 35-10. Multiple Write Functional Flow Diagram
Note:
6462A–ATARM–03-Jun-09
1. It is assumed that this command has been correctly sent (see
2. This field is also accessible in the MCI Block Register (MCI_BLKR).
The following flowchart shows how to manage a multiple write block transfer with the PDC (see
Figure
the contents of the Interrupt Mask Register (MCI_IMR).
35-10). Polling or interrupt method can be used to wait for the end of write according to
Configure the DMA channel X
HDMA_DADDRX = Data Buffer Address
HDMA_BTSIZE = BlockLength/4
Send SET_BLOCKLEN command
Send SELECT/DESELECT_CARD
Set the DMAEN bit
MCI_DMA |= DMAEN
Set the block length (in bytes)
MCI_BLKR |= (BlockLength << 16)
Set the block count (if necessary)
MCI_BLKR |= (BlockCount << 0)
Send WRITE_MULTIPLE_BLOCK
command
Send STOP_TRANSMISSION
Read status register MCI_SR
HDMA_CHEN[X] = TRUE
NOTBUSY = 0?
command (1)
command (1)
(1)
BLKE = 0?
Poll the bit
RETURN
Poll the bit
to select the card
No
No
Figure
(1)
(2)
35-7).
Yes
Yes
AT91SAM9G10
562
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