AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 131
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 131 of 730
- Download datasheet (12Mb)
20.5.2
Register Name:
Address:
Access Type:
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been set to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small. An unreasonably small value breaks every burst and the Bus Matrix spends its time
arbitrating without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMASTR_TYPE: Default Master Type
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in one cycle latency for the first transfer of a burst.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave remains connected to the last mas-
ter that accessed it.
This results in not having the one cycle latency when the last master is trying to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects with the fixed master that
has its index in FIXED_DEFMSTR register.
This results in not having the one cycle latency when the fixed master is trying to access the slave again.
• FIXED_DEFMSTR: Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave.
6462A–ATARM–03-Jun-09
31
23
15
–
–
–
7
Bus Matrix Slave Configuration Registers
30
22
14
MATRIX_SCFG0...MATRIX_SCFG4
0xFFFFEE04
Read-write
–
–
6
29
21
13
–
–
5
28
20
12
–
–
4
SLOT_CYCLE
FIXED_DEFMSTR
27
19
11
–
–
3
26
18
10
–
–
2
AT91SAM9G10
25
17
–
9
–
1
DEFMSTR_TYPE
24
16
–
8
–
0
131
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