AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 41
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 41 of 730
- Download datasheet (12Mb)
11.2.7.1
11.2.7.2
6462A–ATARM–03-Jun-09
Exception Types and Priorities
Status Registers
Exceptions
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see
the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12).
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The
program status registers:
Figure 11-1. Status Register Format
Figure 11-1
The
leged mode. The types of exceptions are:
• CPSR
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operation mode
• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic
• The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
• Mode: five bits to encode the current processor mode
• Fast interrupt (FIQ)
• Normal interrupt (IRQ)
• Data and Prefetched aborts (Abort)
• Undefined instruction (Undefined)
• Software interrupt and Reset (Supervisor)
instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve
DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by
an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the
status of the Q flag.
ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi-
– J = 0: The processor is in ARM or Thumb state, depending on the T bit
– J = 1: The processor is in Jazelle state.
shows the status register format, where:
N Z C V Q
31 30 29 28 27
24
J
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Reserved
I F T
7 6 5
Mode
0
Mode bits
Thumb state bit
FIQ disable
IRQ disable
AT91SAM9G10
41
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