AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 243

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 26-1. Master Clock Controller
26.3
26.4
Figure 26-2. USB Clock Controller
6462A–ATARM–03-Jun-09
Processor Clock Controller
USB Clock Controller
MAINCK
PLLACK
PLLBCK
SLCK
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
Note:
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see
When the PLL B output is stable, i.e., the LOCKB is set:
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
Source
Clock
USB
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48
MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
PMC_MCKR
The ARM Wait for Interrupt mode is entered with CP15 coprocessor operation. Refer to the Atmel
application note,
6217.
CSS
USBDIV
Divider
/1,/2,/4
Optimizing Power Consumption fo AT91SAM9261-based
Master Clock
PMC_MCKR
Prescaler
PRES
UDP
PMC_MCKR
Master
Divider
Clock
MDIV
UDP Clock (UDPCK)
MCK
To the Processor
Clock Controller (PCK)
Figure
AT91SAM9G10
4-7).
Systems, lit. number
243