AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 210
AT91SAM9G10-EK
Manufacturer Part Number
AT91SAM9G10-EK
Description
KIT DEV FOR SAM9G10 ARM
Manufacturer
Atmel
Type
MCUr
Specifications of AT91SAM9G10-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9G10, ARM926EJ-S
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure 23-6. Self-refresh Mode Behavior
23.5.5.2
6462A–ATARM–03-Jun-09
SDRAMC_A[12:0]
SDRAMC_SRR
SDCKE
SDWE
SDCK
SDCS
Write
RAS
CAS
Low-power Mode
SRCB = 1
The SDRAM device must remain in self-refresh mode for a minimum period of t
remain in self-refresh mode for an indefinite period. This is described in
This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register.
Power consumption is greater than in self-refresh mode. All the input and output buffers of the
SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms for a whole device refresh operation). As no auto-refresh operations are performed by the
SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is
faster than in self-refresh mode.
This is described in
Figure
23-7.
Self Refresh Mode
to the SDRAM Controller
Access Request
AT91SAM9G10
T
Figure
XSR
= 3
23-6.
RAS
Row
and may
210
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