AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 170

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

22.8.3
22.8.3.1
22.8.3.2
Figure 22-12. Write Cycle
170
AT91SAM9G10
Write Waveforms
NWE Waveforms
NCS Waveforms
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A
[25:2]
MCK
NWE
NCS
The write protocol is similar to the read protocol. It is depicted in
starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined:
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NCS_WR_SETUP
the NWE falling edge;
rising edge;
the NWE rising edge.
the NCS falling edge.
NCS rising edge;
NCS rising edge.
NWE_SETUP
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NWE_HOLD
NCS_WR_HOLD
Figure
22-12. The write cycle
6462A–ATARM–03-Jun-09