AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 166

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

22.8
22.8.1
Figure 22-8. Standard Read Cycle
22.8.1.1
166
Standard Read and Write Protocols
AT91SAM9G10
Read Waveforms
NRD Waveform
NBS0,NBS1,
NBS2,NBS3,
A0, A1
D[31:0]
A[25:2]
MCK
NRD
NCS
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS3) always have the same timing as the A address bus. NWE represents either the NWE sig-
nal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write
access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..7] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
NCS_RD_SETUP
falling edge;
rising edge;
rising edge.
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
NRD_SETUP
Figure
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
22-8.
NRD_HOLD
NCS_RD_HOLD
6462A–ATARM–03-Jun-09