HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 82

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.3.3
There are 12 external interrupts: IRQ
Interrupts IRQ
IRQ
depending on the settings of bits IEG3 to IEG0 in IEGR1.
When these pins are designated as pins IRQ
edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of
these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1.
These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ
numbers 7 to 4 are assigned to interrupts IRQ
to IRQ
INT Interrupts: INT interrupts are requested by input signals to pins INT
interrupts are detected by either rising edge sensing or falling edge sensing, depending on the
settings of bits INTEG7 to INTEG0 in IEGR2.
When the designated edge is input at pins INT
requesting an interrupt. Recognition of these interrupt requests can be disabled individually by
clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the
I bit to 1 in CCR.
When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is
assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupt-
handling routine must discriminate the interrupt source.
Note: Pins INT
3.3.4
There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2 to 0. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 23 to 9 are
assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip
peripheral modules.
72
0
. These interrupts are detected by either rising edge sensing or falling edge sensing,
3
the designated edge is input or output, the corresponding bit INTFn is set to 1.
(low). Table 3.2 gives details.
External Interrupts
Internal Interrupts
3
to IRQ
3
7
to IRQ
to INT
0
interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
0
0
: Interrupts IRQ
are multiplexed with port 5. Even in port usage of these pins, whenever
3
to IRQ
3
to IRQ
3
to IRQ
0
3
7
and INT
to IRQ
to INT
0
are requested by input signals to pins IRQ
0
in port mode register 1 and the designated
0
. The order of priority is from IRQ
0
7
, the corresponding bit in IRR3 is set to 1,
to INT
0
.
7
to INT
0
. These
0
(high)
3
to