HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 363

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

12.4
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request
register 2 (IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see 3.3, Interrupts.
12.5
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
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input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
Interrupts
Typical Use