HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 359

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

12.2
12.2.1
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to-
digital conversion.
ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not
fixed.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
12.2.2
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Bit 7—Clock Select (CKS): Bit 7 sets the A/D conversion speed.
Bit 7: CKS
0
1
Notes: 1. F-ZTAT version only.
354
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
2. Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a
Register Descriptions
A/D Result Register (ADRR)
A/D Mode Register (AMR)
value of at least 12.4 s.
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
ADR7
CKS
R/W
Conversion Period
62/ø (initial value)
31/ø
R
7
7
0
ADR6
TRGE
R/W
R
6
6
0
ADR5
—
—
R
5
5
1
ADR4
—
—
R
4
4
1
ø = 2 MHz
31 s
15.5 s
ADR3
CH3
R/W
R
3
3
0
Conversion Time
ADR2
ø = 5 MHz
12.4 s
—*
CH2
R/W
R
2
2
0
2
ADR1
CH1
R/W
R
1
1
0
ø = 8 MHz*
7.75 s
—
ADR0
CH0
R/W
R
0
0
0
1