HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 334

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Data Transfer Format: The general data transfer format in synchronous communication is shown
in figure 10.15.
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of the
serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the MSB,
the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity and multiprocessor bits cannot be added.
Clock: Either an internal clock generated by the baud rate generator or an external clock input at
the SCK
in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
328
Serial
clock
Serial
data
Note: High level except in continuous transmission/reception
Don't
care
*
3
pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM
LSB
Bit 0
Figure 10.15 Data Format in Synchronous Communication
Bit 1
One transfer data unit (character or frame)
Bit 2
Bit 3
8 bits
Bit 4
Bit 5
Bit 6
3
pin. Eight pulses
Bit 7
MSB
Don't
care
*