HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 255

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

TCSRX. If OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested.
When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value
selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin. After a reset, the
output from the FTOA or FTOB pin is 0 until the first compare match occurs.
OCRA and OCRB can be written and read by the CPU. Since they are 16-bit registers, data is
transferred between them and the CPU via a temporary register (TEMP). For details see 9.5.3,
CPU Interface.
OCRA and OCRB are initialized to H'FFFF upon reset and in standby mode, watch mode,
subsleep mode, and subactive mode.
Input Capture Registers A to D (ICRA to ICRD)
Input Capture Registers AH to DH (ICRAH to ICRDH)
Input Capture Registers AL to DL (ICRAL to ICRDL)
There are four 16-bit read only input capture registers, ICRA to ICRD.
When the falling edge of an input capture signal is input, the FRC value is transferred to the
corresponding input capture register, and the corresponding input capture flag (ICFA to ICFD) is
set to 1 in TCSRX. If the corresponding input capture interrupt enable bit (ICIAE to ICIDE) is 1 in
TCRX, a CPU interrupt is requested. The valid edge of the input signal can be selected by bits
IEDGA to IEDGD in TCRX.
ICRC and ICRD can also be used as buffer registers for ICRA and ICRB. Buffering is enabled by
bits BUFEA and BUFEB in TCRX.
Figure 9.17 shows the interconnections when ICRC operates as a buffer register of ICRA (when
BUFEA = 1). When ICRC is used as the ICRA buffer, both the rising and falling edges of the
external input signal can be selected simultaneously, by setting IEDGA IEDGC. If IEDGA =
IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9.16.
Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of
Bit
Initial value
Read/Write
the input capture flag (ICF).
15
R
0
ICRAH, ICRBH, ICRCH, ICRDH
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
ICRA, ICRB, ICRC, ICRD
R
9
0
R
8
0
R
7
0
ICRAL, ICRBL, ICRCL, ICRDL
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
247
R
0
0