HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 103

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit read/write register for power-down mode control.
Upon reset, SYSCR2 is initialized to H'E0.
Bits 7 to 5—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
Bit 4—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal (ø
relation to the oscillator clock (ø
to 10 MHz, clear NESEL to 0.
Bit 4: NESEL
0
1
Bit 3—Direct Transfer on Flag (DTON): This bit designates whether or not to make direct
transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP
instruction is executed. The mode to which the transition is made after the SLEEP instruction is
executed depends on a combination of this and other control bits.
94
Bit
Initial value
Read/Write
Description
Sampling rate is ø
Sampling rate is ø
—
—
7
1
—
—
6
1
OSC
W
) generated by the system clock pulse generator. When ø
) generated by the subclock pulse generator is sampled, in
OSC
OSC
/16
/4
—
—
5
1
NESEL
R/W
4
0
DTON
R/W
3
0
MSON
R/W
2
0
SA1
R/W
1
0
(initial value)
SA0
R/W
OSC
0
0
= 2