HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 264

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 1—Output Level A (OLVLA): Bit 1 selects the output level that is output at pin FTOA by
compare match A (when FRC matches OCRA).
Bit 1: OLVLA
0
1
Bit 0—Output Level B (OLVLB): Bit 0 selects the output level that is output at pin FTOB by
compare match B (when FRC matches OCRB).
Bit 0: OLVLB
0
1
9.5.3
FRC, OCRA, OCRB, and ICRA to ICRD are 16-bit registers, but the CPU is connected to the on-
chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore
uses an 8-bit temporary register (TEMP).
These registers should always be accessed 16 bits at a time. If two consecutive byte-size MOV
instructions are used, the upper byte must be accessed first and the lower byte second. Data will
not be transferred correctly if only the upper byte or only the lower byte is accessed.
256
CPU Interface
Description
Low level
High level
Description
Low level
High level
(initial value)
(initial value)