HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 76

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Interrupt Enable Register 1 (IENR1)
IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1
is initialized to H'10.
Bit 7—Timer B1 Interrupt Enable (IENTB1): Bit 7 enables or disables timer B1 overflow
interrupt requests.
Bit 7: IENTB1
0
1
Bit 6—Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt
requests.
Bit 6: IENTA
0
1
Bit 5—Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—IRQ
to IRQ
Bit n: IENn
0
1
66
Bit
Initial value
Read/Write
0
interrupt requests.
3
IENTB1
to IRQ
R/W
Description
Disables timer B1 interrupt requests
Enables timer B1 interrupt requests
Description
Disables timer A interrupt requests
Enables timer A interrupt requests
Description
Disables interrupt requests from pin IRQ
Enables interrupt requests from pin IRQ
7
0
0
Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable IRQ
IENTA
R/W
6
0
—
—
5
0
—
—
4
1
n
n
IEN3
R/W
3
0
IEN2
R/W
2
0
IEN1
R/W
1
0
(initial value)
(initial value)
(initial value)
(n = 3 to 0)
IEN0
R/W
0
0
3