HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 285

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

9.6.3
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (ø/8192).
When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in
WDON, TCW starts counting up (two write accesses to TCSRW are necessary in order to operate
the watchdog timer). When the TCW count value reaches H'FF, the next clock input causes the
watchdog timer to overflow and generates an internal reset signal. The internal reset signal is
output for 512 clock cycles of the ø
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.36 shows an example of watchdog timer operations.
Example: ø = 4 MHz and the desired overflow period is 30 ms.
The value set in TCW should therefore be 256 – 15 = 241 (H'F1).
Internal reset
signal
TCW count
value
H'FF
H'00
Timer Operation
4
8192
10
Figure 9.36 Typical Watchdog Timer Operations (Example)
H'F1
6
H'F1 written
in TCW
30
10
–3
Start
= 14.6
OSC
clock. It is possible to write to TCW, causing TCW to
H'F1 written in TCW
512 ø
Reset
OSC
TCW overflow
clock cycles
277