HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 129

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.5.2
EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure.
EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby
mode, and when 12 V is not applied to FV
block is selected and can be programmed and erased. The erase block map is shown in figure 6.8,
and the correspondence between bits and erase blocks is shown in table 6.9.
Note: * Word access cannot be used on this register; byte access must be used. For information on
Bits 7 to 4—Reserved: Bits 7 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bits 3 to 0—Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be
programmed and erased.
Bits 3 to 0:
LB3 to LB0
0
1
120
Bit
Initial value
Read/Write
access to this register, see note 11 in section 6.9, Flash Memory Programming and Erasing
Precautions. LB3 is invalid in the H8/3643F, and LB3 and LB2 are invalid in the H8/3642AF.
Erase Block Register 1 (EBR1)
Description
Block LB3 to LB0 is not selected
Block LB3 to LB0 is selected
—
—
7
1
—
—
6
1
—
—
5
1
PP
. When a bit in EBR1 is set to 1, the corresponding
—
—
4
1
R/W*
LB3
3
0
R/W*
LB2
2
0
R/W*
LB1
1
0
(initial value)
R/W*
LB0
0
0