HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 261

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 1: OVF
0
1
Bit 0—Counter Clear A (CCLRA): Bit 0 selects whether or not to clear FRC by compare match
A (when FRC matches OCRA).
Bit 0: CCLRA
0
1
Timer Control Register X (TCRX)
TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals,
enables buffering, and selects the FRC clock source.
TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7—Input Edge Select A (IEDGA): Bit 7 selects the rising or falling edge of the input capture
A input signal (FTIA).
Bit 7: IEDGA
0
1
Bit 6—Input Edge Select B (IEDGB): Bit 6 selects the rising or falling edge of the input capture
B input signal (FTIB).
Bit 6: IEDGB
0
1
Bit
Initial value
Read/Write
IEDGA
Description
Clearing conditions:
After reading OVF = 1, cleared by writing 0 to OVF
Setting conditions:
Set when the FRC value overflows from H'FFFF to H'0000
Description
FRC is not cleared by compare match A
FRC is cleared by compare match A
R/W
Description
Falling edge of input capture A is captured
Rising edge of input capture A is captured
Description
Falling edge of input capture B is captured
Rising edge of input capture B is captured
7
0
IEDGB
R/W
6
0
IEDGC
R/W
5
0
IEDGD
R/W
4
0
BUFEA
R/W
3
0
BUFEB
R/W
2
0
CKS1
R/W
1
0
(initial value)
(initial value)
(initial value)
(initial value)
CKS0
R/W
0
0
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