HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 348

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

10.3.8
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
2. Operation when a number of receive errors occur simultaneously
Table 10.17 SSR Status Flag States and Receive Data Transfer
RDRF* OER
1
0
0
1
1
0
1
O: Receive data is transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception.
342
: Receive data is not transferred from RSR to RDR.
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared
to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has
not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to
TDR once only (not two or more times).
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to
the states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR
will not be performed, and the receive data will be lost.
SSR Status Flags
1
0
0
1
1
0
1
Application Notes
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
Receive Data Transfer
(RSR
O
O
O
RDR)
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error