HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 145

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.7.6
Flowchart for Erasing One Block
136
Address + 1
Erase Flowcharts and Sample Programs
Write 0 data in all addresses to be erased
No
(set bit for block to be erased to 1)
Dummy write to verify address
(clear bit for erased block to 0)
Enable watchdog timer
Set block start address as
Clear erase block register
Select erase-verify mode
Disable watchdog timer
address
Set erase block register
(flash memory latches
(E bit = 1 in FLMCR)
Select erase mode
(read data H'FF?)
Wait (t
Wait (t
Last address?
Wait (x) ms
End of erase
verify address
Clear EV bit
Clear E bit
(prewrite)
(EV bit = 1)
Verify
address)
Start
n = 1
vs1
vs2
OK
Yes
) s
) s
*4
*1
*5
*6
*6
*2
Figure 6.15 Erase Flowchart
*3
NG
Erasing halts
Clear EV bit
Erase error
n
Notes: 1. Program all addresses to be erased by
N?
Yes
*6
2. Set the watchdog timer overflow interval to
3. For the erase-verify dummy write, write H'FF
4. For the erase-verify operation, read the data
5. Erase time x is successively incremented to
6. t
following the prewrite flowchart.
the initial value shown in table 6.13.
using a byte transfer instruction.
using a byte transfer instruction. When
erasing multiple blocks, clear the erase block
register bits for erased blocks and perform
additional erasing only for unerased blocks.
initial set value x 2n-1 (n = 1 to 4), and is fixed
from the 4th time onward. An initial value of
6.25 ms or less should be set, and the time
for one erasure should be 50 ms or less.
t
N:
vs1
vs2
: 4 s or more
: 2 s or more
602 (set N so that the total erase time
does not exceed 30 s)
End of erase-verify
No
Double the erase time
(x
n + 1
n
2
4?
No
n
x)
Yes